The disclosure relates generally to integrated circuits (ICs), and, more particularly, to a structure and method for cooling a three dimensional (3D) chip stack.
To pack multiple semiconductor integrated chips into a compact device, such as a cell phone, PDA, GPS, or laptop computer, packaging with 3D chip stack becomes increasingly popular. A 3D chip stack allows designers or assemblers greater flexibility to stack various chip technologies into small, high performance functional blocks. For example, flash memories combined with SRAM, DRAM, DSP, or microprocessors are all candidates for this 3D chip stack technique. One can even stack silicon chips with III-V compound chips, which can not be easily fabricated monolithically.
Stacking ultra-thin chips may be interconnected using wire-bonding, or by a combination of wire-bonding and flip-chip assembly. The use of wire-bonding as the exclusive means of interconnection is somewhat restrictive, since the number of stacked die that may be wire-bonded may be limited to only three. Some techniques also allow for stacking of chips with largely varying dimensions, as well as the integration of thin-film passive components in a 3D interconnect stack.
3D chip stacks may need to include a cooling mechanism. When two chips are bonded together, one side of each chip is exposed to the air, which can be cooled by the ambient cool air. However, when more chips are bonded together, such as in a 3D chip stack, chips in the middle are not exposed to ambient air. Lack of exposure to ambient air for middle chips may not be a problem for chips that consume less power. For example, memory chips generally consume less power than high-speed CPU chips, and therefore, memory chips generate less heat, than CPU chips. Therefore, a separate cooling mechanism would not necessarily be required for a 3D memory chip stack. For high-speed CPU chips, which consume more power, and therefore generate more heat, a separate cooling mechanism may be necessary for a 3D CPU chip stack.